Clock signals are important to the functioning of radio communication systems. In such systems, clock signals are required for various purposes, such as synchronization. Without reliable, accurate clock signals, radio communication systems cannot work properly.
In many radio communication devices, such as mobile terminals, radio frequency (RF) clock signals are usually generated by certain on-chip components, e.g., by phase locked loops (PLLs) which can lock to an external crystal resonator as a reference clock input with various dividing factors. Normally, for different components of the device running at different frequencies, multiple PLLs are required in the integrated circuit. For example, for transmitter and receiver circuits of a mobile terminal running at different frequencies, at least two PLLs are usually required.
Multi-function mobile terminals have become popular in the recent years. As mobile terminals become more and more advanced and complicated, multiple RF clock signals are needed for different applications, such as Wireless LAN, Bluetooth, GPS, cellular communication, etc. Moreover, in some newly suggested radio standards, such as 3GPP TS 36.101 v.10.4.0 (2011-09), in order to increase communication data rate, carrier aggregation is suggested, where two or more RF clock signals may be required for the receiver and the transmitter, respectively.
However, creating RF clock signals using multiple PLLs is not an easy task, especially for on-chip integrated solutions. Among others, crosstalk between multiple PLLs is a serious problem.
FIG. 1 illustrates the crosstalk problem between PLLs in a conceptual manner. As suggested in FIG. 1, two PLLs are integrated into one chip. Each PLL comprises a controlled oscillator (CO) to generate the respective clock signal. The controlled oscillator may be an LC-based voltage controlled oscillator (VCO), which comprises an inductor L and a capacitor C, as shown in FIG. 1. This also can be applied to digitally controlled oscillators where inductor and capacitor are employed. Since the coupling coefficient, indicated as K12, of the inductors (L1 and L2) of the two respective VCOs (VCO1 and VCO2) is not zero due to electromagnetic radiation. Crosstalk/leakage (including electromagnetic coupling and interference) may be generated between the two PLLs, thus causing an adverse effect to the generation of the clock signals. The interference can be caused by factors such as poor supply de-coupling, unwanted coupling effects of passive and active devices, like package and ESD protection circuits, etc.
More understanding of the crosstalk problem can be gathered from FIG. 2, which shows, in the frequency domain, the clock signals generated by the two PLLs, the crosstalk signals existing there between, and the actual output of the two PLLs.
Specifically, in FIG. 2, C1 and C2 indicate the clock signals generated by VCO1 and VCO2, respectively, L1 indicates the unwanted crosstalk signal from VCO1 to VCO2, and L2 represents the unwanted crosstalk signal in the reverse direction, i.e., from VCO2 to VCO1. D21 and D12 are power ratios between the power of the wanted clock signals and the power of the respective unwanted crosstalk signals.
When multiple PLLs are integrated into a single chip, they will interfere with each other, and the crosstalk between their VCOs will become a critical issue which can degrade the performance of the PLLs. For example, the PLLs will suffer from increased phase noise, frequency shift, and difficulty in locking. In the worst case, the PLLs may fail to perform the locking. The crosstalk depends on several factors. Two typical factors are the physical distance and the frequency difference between two PLLs in question.
One way to reduce the crosstalk between multiple PLLs is to physically separate the PLLs apart. For instance, with reference to the LC-based PLLs illustrated in FIG. 1, the two inductors L1 and L2 of the respective controlled oscillators can be positioned on the same chip but far from each other.
A result from electromagnetic simulation for the coupling between the two inductors is shown in FIG. 3, where the normalized distance is the ratio of separation distance divided by the diameter of the inductors, and the coupling coefficient is the isolation between the two inductors.
Although this separation solution can reduce the crosstalk between multiple PLLs on a chip, it is sometimes impractical due to the requirement of a large silicon area. This is especially true where the chip for hosting the PLLs must be small. Thus, the solution could become expensive, in particular for implementations requiring deep nanometer CMOS techniques. Moreover, the metal usage for routing among the separation area between the two inductors could make the situation even worse.